Computer System Architecture

Digital logic & number systems

A number system is defined by its base and its digits. Binary uses base 2 with digits 0 and 1, octal base 8, decimal base 10, and hexadecimal base 16 with digits 0 to 9 and letters A to F for values 10 to 15. Conversion between bases follows place values: each digit is multiplied by the base raised to its position power, counting from zero at the rightmost integer digit, and fractional digits use negative powers. Binary to octal groups bits in threes from the binary point, binary to hexadecimal groups bits in fours, and decimal to another base uses repeated division by the base for the integer part and repeated multiplication by the base for the fraction, recording remainders or integer parts in order. These conversions are routine examination arithmetic, and errors usually come from grouping in the wrong direction or misreading hexadecimal letters.

Signed integers are commonly stored in two complement form. The one complement of a binary number flips every bit, and the two complement adds one to the one complement. Two complement representation has a single zero, a range from minus 2 to the power (n minus 1) to plus 2 to the power (n minus 1) minus 1 for n bits, and addition and subtraction use the same adder circuit, with overflow detected when the carry into the sign bit differs from the carry out of it. Floating-point numbers follow the form sign times mantissa times base to the exponent, with a biased exponent so that exponents can be compared as unsigned integers, and a normalised mantissa with an implicit leading one in the usual binary format. Precision is limited by mantissa width, range by exponent width, and rounding and overflow are consequences of finite representation, not programming errors.

Boolean algebra works on variables taking values 0 and 1, with operations AND, OR, and NOT, governed by identity, annihilator, idempotent, complement, commutative, associative, distributive, absorption, and De Morgan laws. A Boolean function can be written in sum-of-products form, a disjunction of product terms, or product-of-sums form, a conjunction of sum terms. Canonical forms use minterms, product terms covering exactly one combination of variables, and maxterms, the dual sum terms. A Karnaugh map arranges truth-table cells so adjacent cells differ in one variable, letting you group powers of two cells (1, 2, 4, 8) to eliminate variables that change within the group. Essential prime implicants must appear in every minimal cover, and do-not-care conditions may be treated as 0 or 1 whichever simplifies the result, but they must never be required to be covered.

Combinational circuits have outputs determined solely by current inputs. A half adder adds two bits giving sum and carry; a full adder adds two bits plus a carry-in. A multiplexer selects one of many inputs using select lines, so a 4-to-1 multiplexer needs two select lines, and a demultiplexer reverses the operation. A decoder activates exactly one output for each input combination, and an encoder does the reverse; a priority encoder resolves simultaneous requests. Sequential circuits add feedback and a clock, so outputs depend on current inputs and stored state. An SR flip-flop sets or resets on its inputs, a JK flip-flop removes the invalid SR condition by toggling, a D flip-flop copies its input to its output on the clock edge, and a T flip-flop toggles when its input is 1. Registers store multi-bit values, shift registers move bits serially, and counters cycle through states: a ripple counter chains flip-flop clocks with propagation delay accumulating, while a synchronous counter clocks all flip-flops together.

CPU, memory & I/O organisation

The central processing unit contains the arithmetic logic unit, which performs arithmetic and logical operations, the control unit, which directs data movement and interprets instructions, and registers, the fastest storage in the machine. Key registers include the program counter holding the address of the next instruction, the instruction register holding the current instruction, the accumulator or general-purpose registers holding operands and results, the memory address register, and the memory buffer register. The instruction cycle has four phases: fetch the instruction from memory using the program counter, decode it to identify the operation and operands, execute it in the arithmetic logic unit or through a memory or input-output operation, and store the result, after which the program counter advances. Interrupts may be recognised between instructions, with the processor saving state, jumping to a handler, and resuming afterwards.

The control unit may be hardwired, using fixed combinational logic that is fast but hard to change, or microprogrammed, using stored microinstructions that are slower but flexible and easier to modify. Memory is organised as a hierarchy because no single technology is simultaneously fast, large, and cheap: registers are fastest and smallest, cache is fast and moderately sized, main memory is larger and slower, and secondary storage is largest and slowest. The principle of locality explains why the hierarchy works: temporal locality means recently used items are likely to be reused, and spatial locality means nearby items are likely to be used soon, so caches and prefetching pay off. A cache holds blocks, also called lines, of main memory. In direct mapping, each block maps to exactly one cache line, giving fast lookup but many conflict misses. In fully associative mapping, a block may go in any line, giving fewest conflicts but requiring parallel comparison of all tags. In set-associative mapping, a block maps to one set but may occupy any line within it, balancing speed and flexibility; a 2-way or 4-way set-associative cache is the common compromise. Replacement policies such as least recently used, first-in first-out, and random decide which block to evict, and write policies decide whether writes update main memory immediately (write-through) or only on eviction (write-back, with a dirty bit).

Average memory access time combines hit time, hit rate, and miss penalty: AMAT equals hit time plus miss rate times miss penalty. If a cache has several levels, the miss penalty of one level is the access time of the next, so the formula nests. Virtual memory gives each program the illusion of a large private address space by paging: virtual addresses split into a page number and an offset, a page table maps pages to frames in physical memory, and pages not present cause a page fault that loads the page from disk. The translation lookaside buffer is a small fast cache of recent page-table entries; a TLB hit avoids a full page-table walk, while a TLB miss costs extra memory accesses. Effective access time with a TLB therefore weights the TLB hit time against the miss cost, exactly like a cache calculation.

Input and output organisation must move data without tying up the processor unnecessarily. Programmed input-output makes the processor poll device status and transfer every byte, which is simple but wasteful. Interrupt-driven input-output lets the device signal readiness, so the processor works on other tasks until interrupted, but each transfer still passes through the processor. Direct memory access goes further: a DMA controller takes over the bus, transfers a whole block between device and memory, and interrupts the processor only once when the block is complete, freeing the processor for other work. DMA modes include burst mode, which holds the bus for the whole block, and cycle stealing, which interleaves DMA cycles with processor cycles. Interrupts themselves are classified as maskable or non-maskable, vectored or non-vectored, and internal or external, and interrupt priority and nesting decide which handler runs when several requests arrive together.

Instruction formats & RISC/CISC

An instruction encodes an operation code, or opcode, plus operands. Instruction formats vary in length and in the number of explicit operand addresses. A three-address instruction names two sources and a destination, as in ADD R1, R2, R3, and is expressive but long. A two-address instruction overwrites one source with the result, a one-address instruction uses an accumulator implicitly, and a zero-address instruction works on a stack, with operations popping operands and pushing results. Fixed-length formats simplify decoding and pipelining but waste bits on short instructions, while variable-length formats save space at the cost of complex decoding. Addressing modes determine how the operand address is computed from the instruction fields. Immediate addressing embeds the operand value itself, direct addressing gives the operand address, indirect addressing gives the address of the address, register addressing names a register, register-indirect addressing uses a register as a pointer, indexed addressing adds an index register to a base address for array access, and relative addressing adds an offset to the program counter for branches. Effective address calculations and the number of memory accesses per mode are standard examination questions: immediate needs no memory access for the operand, direct needs one, and indirect needs at least two.

Reduced instruction set computing, RISC, uses a small set of simple fixed-length instructions, load-store architecture in which only load and store instructions access memory, many registers, hardwired control, and heavy reliance on compiler optimisation and pipelining. Complex instruction set computing, CISC, uses many variable-length instructions, memory-to-memory operations, fewer registers, microprogrammed control, and complex instructions that do more work each, at the cost of harder decoding and pipelining. Neither is universally better: RISC tends to give higher clock rates and simpler pipelines, CISC tends to give denser code and simpler compilers for hand-written assembly, and modern processors often blend the two, decoding CISC instructions into RISC-like internal operations.

Pipelining overlaps instruction execution by dividing it into stages, typically fetch, decode, execute, memory access, and write-back, so that while one instruction executes, the next is decoded and another is fetched. In the ideal case a pipeline completes one instruction per cycle after filling, giving a speedup approaching the number of stages, but hazards reduce this. Structural hazards arise when two stages need the same resource in the same cycle, for example a single memory port for fetch and data access, and are fixed by duplicating resources or stalling. Data hazards arise when an instruction needs a result not yet written back, and are handled by forwarding (bypassing the result directly to the needing stage), by stalling with bubbles, or by compiler reordering. Control hazards arise from branches, whose target is unknown until late in the pipeline, and are handled by stalling, by branch prediction, or by delayed branching. Distinguish these three hazard types by their cause: resource conflict, data dependence, or control flow. A final organisation point is bus structure: a system bus carries address, data, and control signals between processor, memory, and input-output, and bus width and clock rate bound transfer bandwidth, which is why DMA and cache design matter as much as raw processor speed.

Cache mapping policies compared

RISC versus CISC

Flip-flops compared

Pipeline hazards compared