CPU, memory & I/O organisation

A CPU repeats one loop forever: fetch an instruction from memory, decode it, execute it, and move on. Performance comes from doing that loop cleverly. Pipelining overlaps the stages of successive instructions the way an assembly line overlaps cars, and caching keeps frequently used data close to the CPU. Worked example: a cache with a 95% hit ratio, a 5 ns hit time and an 80 ns miss penalty has an average access time of 0.95 x 5 + 0.05 x (5 + 80) = 4.75 + 4.25 = 9 ns. Note the miss still pays the hit time first — the CPU checks the cache, misses, and only then goes to main memory. That single detail decides many numerical questions.